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ds05-11414-2e fujitsu semiconductor data sheet memory mobile fcram tm cmos 32m bit (2 m word 16 bit) mobile phone application specific memory mb82dps02183b -85/-85l cmos 2,097,152-word x 16 bit fast cycle random access memory with low power sram interface n description the fujitsu mb82dps02183b is a cmos fast cycle random access memory (fcram*) with asynchronous static random access memory (sram) interface containing 33,554,432 storages accessible in a 16-bit format. this mb82dps02183b is suited for mobile applications such as cellular handset and pda. *: fcram is a trademark of fujitsu limited, japan n features ? asynchronous sram interface ? fast access cycle time : t ce = 85 ns max ? 8 words page access capability : t pa a = 25 ns max ? low voltage operating condition : v dd = + 1.65 v to + 1.95 v ? wide operating temperature : t a = - 30 c to + 85 c ? byte control by lb and ub (continued) n pac k ag e 48-ball plastic fbga (bga-48p-m18)
mb82dps02183b -85/-85l 2 (continued) ? low power consumption : i dda1 = 25 ma max i dds1 = 200 m a max 100 m a max (l version) ? various partial power down mode : sleep 4 m-bit partial 8 m-bit partial 16 m-bit partial
mb82dps02183b -85/-85l 3 n pin assignment n pin description pin name description a 20 to a 0 address input ce 1 chip enable (low active) ce2 chip enable (high active) we write enable (low active) oe output enable (low active) lb lower byte control (low active) ub upper byte control (low active) dq 8 to dq 1 lower byte data input/output dq 16 to dq 9 upper byte data input/output v dd power supply v ss ground n.c. no connection a b c d e f g h lb dq 9 dq 10 v ss v dd dq 15 dq 16 a 18 oe ub dq 11 dq 12 dq 13 dq 14 a 19 a 8 a 0 a 3 a 5 a 17 n.c. a 14 a 12 a 9 a 1 a 4 a 6 a 7 a 16 a 15 a 13 a 10 a 2 ce1 dq 2 dq 4 dq 5 dq 6 we a 11 ce2 dq 1 dq 3 v dd v ss dq 7 dq 8 a 20 16 5 4 3 2 (top view) (bga-48p-m18)
mb82dps02183b -85/-85l 4 n block diagram v dd v ss ce2 ce1 we lb ub oe a 20 to a 0 dq 8 to dq 1 dq 16 to dq 9 address latch & buffer row decoder memory cell array 33,554,432 bit output data control sense/switch column/decoder address latch & buffer input data latch & control i/o buffer power control timing control
mb82dps02183b -85/-85l 5 n function truth table notes : l = v il , h = v ih , x can be either v il or v ih , high-z = high impedance *1 : should not be kept this logic condition longer than 1 m s. *2 : power down mode can be entered from standby state and all dq pins are in high-z state. data retention depends on the selection of power down program. refer to power down program for the detail. *3 : can be either v il or v ih but must be valid before read or write. *4 : oe can be v il during write operation if the following conditions are satisfied; (1) write pulse is initiated by ce 1 (refer to ce 1 controlled write timing) , or cycle time of the previous operation cycle is satisfied. (2) oe stays v il during write cycle. mode ce2 ce 1we oe lb ub a 20 to a 0 dq 8 to dq 1 dq 16 to dq 9 standby (deselect) hhxxxx x high-zhigh-z output disable* 1 hl h h x x *3 high-z high-z output disable (no read) hl h h valid high-z high-z read (upper byte) h l valid high-z output valid read (lower byte) l h valid output valid high-z read (word) l l valid output valid output valid no write lh* 4 h h valid invalid invalid write (upper byte) h l valid invalid input valid write (lower byte) l h valid input valid invalid write (word) l l valid input valid input valid power down* 2 lxxxxx x high-zhigh-z
mb82dps02183b -85/-85l 6 n power down power down the power down is to enter low power idle state when ce2 stays low. the mb82dps02183b has four power down mode, sleep, 4 m partial, 8 m partial, and 16 m partial. these can be programmed by series of read/write operation. each mode has following features. the default state is sleep and it is the lowest power consumption but all data will be lost once ce2 is brought to low for power down. it is not required to program to sleep mode after power-up. power down program sequence the program requires total 6 read/write operation with unique address and data. between each read/write operation requires that device be in standby mode. following table shows the detail sequence. the first cycle is to read from most significant address (msb) . the second and third cycle are to write back the data (rda) read by first cycle. if the second or third cycle is written into the different address, the program is cancelled and the data written by the second or third cycle is valid as a normal write operation. the forth and fifth cycle is to write the data key for program. the data of forth cycle must be all 0s and data of fifth cycle is a data key for mode selection. if the forth or fifth cycle is written into different address, the program is also cancelled but write data may not be written as normal write operation. the last cycle is to read from specific address key for mode selection. the both data key written by fifth cycle and address key must be the same mode for proper programming. once this program sequence is performed from a partial mode to other partial mode, the write data may be lost. so, it should perform this program prior to regular read/write operation if partial mode is used. address key the address key has following format. mode data retention retention address sleep (default) no n/a 4 m partial 4 m bit 00000h to 3ffffh 8 m partial 8 m bit 00000h to 7ffffh 16 m partial 16 m bit 00000h to fffffh cycle # operation address data 1st read 1fffffh (msb) read data (rda) 2nd write 1fffffh rda 3rd write 1fffffh rda 4th write 1fffffh 0000h 5th write 1fffffh data key 6th read address key read data (rdb) mode address a 20 a 19 a 18 to a 0 binary sleep (default) 1 1 1 1fffffh 4 m partial 0 1 1 0fffffh 8 m partial 1 0 1 17ffffh 16 m partial 0 0 1 07ffffh
mb82dps02183b -85/-85l 7 data key the data key has following format. the upper byte of data code may be ignored and it is just for recommendation to write 0s to upper byte for future compatibility. mode data dq 16 to dq 9 dq 8 to dq 2 dq 1 dq 0 sleep (default) 0 0 1 1 4 m partial 0 0 1 0 8 m partial 0 0 0 1 16 m partial 0 0 0 0
mb82dps02183b -85/-85l 8 n absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions *1 : all voltage are referenced to vss. *2 : maximum dc voltage on input and i/o pins are v dd + 0.2 v. during voltage transitions, inputs may overshoot to v dd + 1.0 v for periods of up to 5 ns. *3 : minimum dc voltage on input or i/o pins is - 0.3 v. during voltage transitions, inputs may undershoot v ss to - 1.0 v for periods of up to 5 ns. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit min max voltage of v dd supply relative to vss v dd - 0.5 + 3.6 v voltage at any pin relative to vss v in , v out - 0.5 + 3.6 v short circuit output current i out - 50 + 50 ma storage temperature t stg - 55 + 125 c parameter symbol value unit min max supply voltage* 1 v dd 1.65 1.95 v v ss 00v high level input voltage * 1 , * 2 v ih v dd 0.8 v dd + 0.2 v low level input voltage * 1 , * 3 v il - 0.3 v dd 0.2 v ambient temperature t a - 30 + 85 c
mb82dps02183b -85/-85l 9 n pin capacitance (f = 1 mhz, t a = + 25 c) parameter symbol test conditions value unit min typ max address input capacitance c in1 v in = 0 v ?? 5pf control input capacitance c in2 v in = 0 v ?? 5pf data input/output capacitance c i/o v io = 0 v ?? 8pf
mb82dps02183b -85/-85l 10 n electrical characteristics (at recommended operating conditions unless otherwise noted.) 1. dc characteristics notes : all voltages are referenced to vss. dc characteristics are measured after following power-up timing. i out depends on the output load conditions. parameter symbol test conditions value unit min max input leakage current i li v ss v in v dd - 1.0 + 1.0 m a output leakage current i lo 0 v v out v dd , output disable - 1.0 + 1.0 m a output high voltage level v oh v dd = v dd min, i oh = - 0.5 ma 1.4 ? v output low voltage level v ol i ol = 1 ma ? 0.4 v v dd power down current i ddps v dd = v dd max, v in = v ih or v il , ce2 0.2 v sleep ? 30 m a l version ? 10 m a i ddp4 4 m partial ? 80 m a l version ? 45 m a i ddp8 8 m partial ? 100 m a l version ? 55 m a i ddp16 16 m partial ? 130 m a l version ? 70 m a v dd standby current i dds v dd = v dd max, v in = v ih or v il , ce 1 = ce2 = v ih ? 5ma l version ? 1.5 ma i dds1 v dd = v dd max, v in 0.2 v or v il 3 v dd - 0.2 v, ce 1 = ce2 3 v dd - 0.2 v ? 200 m a l version ? 100 m a v dd active current i dda1 v dd = v dd max, v in = v ih or v il , ce 1 = v il and ce2 = v ih , i out = 0 ma t rc /t wc = minimum ? 25 ma i dda2 t rc /t wc = 1 m s ? 3ma v dd page read current i dda3 v dd = v dd max, v in = v ih or v il , ce 1 = v il and ce2 = v ih , i out = 0 ma, t prc = min ? 10 ma
mb82dps02183b -85/-85l 11 2. ac characteristics (1) read operation *1 : maximum value is applicable if ce 1 is kept at low without change of address input of a 20 to a 3 . *2 : address should not be changed within minimum t rc . *3 : the output load 50 pf with 50 w termination to v dd 0.5 v. *4 : the output load 5 pf without any other load. *5 : applicable to a 20 to a 3 when ce 1 is kept at low. *6 : applicable only to a 2 , a 1 and a 0 when ce 1 is kept at low for the page address access. *7 : in case page read cycle is continued with keeping ce 1 stays low, ce 1 must be brought to high within 4 m s. in other words, page read cycle must be closed within 4 m s. *8 : applicable when at least two of address inputs among applicable are switched from previous state. *9 : t rc (min) and t prc (min) must be satisfied. parameter symbol -85/-85l unit notes min max read cycle time t rc 85 1000 ns *1, *2 ce 1 access time t ce ? 85 ns *3 oe access time t oe ? 50 ns *3 address access time t aa ? 85 ns *3, *5 lb /ub access time t ba ? 35 ns *3 page address access time t paa ? 25 ns *3, *6 page read cycle time t prc 30 1000 ns *1, *6, *7 output data hold time t oh 5 ? ns *3 ce 1 low to output low-z t clz 5 ? ns *4 oe low to output low-z t olz 0 ? ns *4 lb /ub low to output low-z t blz 0 ? ns *4 ce 1 high to output high-z t chz ? 20 ns *3 oe high to output high-z t ohz ? 20 ns *3 lb /ub high to output high-z t bhz ? 20 ns *3 address setup time to ce 1 low t asc - 5 ? ns address setup time to oe low t aso 12 ? ns address invalid time t ax ? 10 ns *5, *8 address hold time from ce 1 high t chah - 5 ? ns *9 address hold time from oe high t ohah - 5 ? ns ce 1 high pulse width t cp 15 ? ns
mb82dps02183b -85/-85l 12 (2) write operation *1 : maximum value is applicable if ce 1 is kept at low without any address change. *2 : minimum value must be equal or greater than the sum of write pulse (t cw , t wp or t bw ) and write recovery time (t wrc , t wr or t br ) . *3 : write pulse is defined from high to low transition of ce 1, we , or lb /ub , whichever occurs last. *4 : applicable for byte mask only. byte mask setup time is defined to the high to low transition of ce 1 or we whichever occurs last. *5 : applicable for byte mask only. byte mask hold time is defined from low to high transition of ce 1 or we whichever occurs first. *6 : write recovery is defined from low to high transition of ce 1, we , or lb /ub , whichever occurs first. *7 : if oe is low after minimum t ohcl , read cycle is initiated. in other words, oe must be brought to high within 5 ns after ce 1 is brought to low. once read cycle is initiated, new write pulse should be input after minimum t rc is met. *8 : if oe is low after new address input, read cycle is initiated. in other words, oe must be brought to high at the same time or before new address valid. once read cycle is initiated, new write pulse should be input after minimum t rc is met. parameter symbol -85/-85l unit notes min max write cycle time t wc 85 1000 ns *1, *2 address setup time t as 0 ? ns *2 ce 1 write pulse width t cw 50 ? ns *3 we write pulse width t wp 50 ? ns *3 lb /ub write pulse width t bw 50 ? ns *3 lb /ub byte mask setup time t bs - 5 ? ns *4 lb /ub byte mask hold time t bh 5 ? ns *5 ce 1 write recovery time t wrc 15 ? ns *6 we write recovery time t wr 15 1000 ns *6 lb /ub write recovery time t br 15 1000 ns *6 data setup time t ds 20 ? ns data hold time t dh 0 ? ns oe high to ce 1 low setup time for write t ohcl - 5 ? ns *7 oe high to address setup time for write t oes 0 ? ns *8 lb and ub write pulse overlap t bwo 20 ? ns ce 1 high pulse width t cp 15 ? ns
mb82dps02183b -85/-85l 13 (3) power down parameters *1 : applicable also to power-up. *2 : applicable when 4 m, 8 m, and 16 m partial mode is programmed. (4) other timing parameters *1 : some data might be written into any address location if t chwx (min) is not satisfied. *2 : the input transition time (t t ) at ac testing is 5 ns as shown in below. if actual t t is longer than 5 ns, it may violate ac specification of some timing parameters. (5) ac test conditions parameter symbol value unit note min max ce2 low setup time for power down entry t csp 10 ? ns ce2 low hold time after power down entry t c2lp 85 ? ns ce 1 high hold time following ce2 high after power down exit [sleep mode only] t chh 300 ?m s*1 ce 1 high hold time following ce2 high after power down exit [not in sleep mode] t chhp 1 ?m s*2 ce 1 high setup time following ce2 high after power down exit t chs 0 ? ns parameter symbol value unit note min max ce 1 high to oe invalid time for standby entry t chox 10 ? ns ce 1 high to we invalid time for standby entry t chwx 10 ? ns *1 ce 1 high hold time following ce2 high after power-up t chh 300 ?m s input transition time t t 125ns*2 description symbol test setup value unit note input high level v ih ? v dd 0.8 v input low level v il ? v dd 0.2 v input timing measurement level v ref ? v dd 0.5 v input transition time t t between v il and v ih 5ns
mb82dps02183b -85/-85l 14 v dd v ss 0.1 m f 50 pf output 50 w device under test v dd 0.5 v ac measurement output load circuit
mb82dps02183b -85/-85l 15 n timing diagrams (1) read timing #1 (basic timing) t rc t ce t asc t chah t cp t chz t ohz t oe t ba t blz t olz t clz t bhz t oh t asc ce1 oe dq lb , ub note : ce2 and we must be high for entire read cycle. valid data output (output) address address valid
mb82dps02183b -85/-85l 16 (2) read timing #2 (oe & address access) note : ce2 and we must be high for entire read cycle. ce1 oe dq t rc t rc t aso t oe t ohz t olz t oh t oh t ohah t aa t aa t ax lb, ub low valid data output (output) address valid address valid address valid data output
mb82dps02183b -85/-85l 17 (3) read timing #3 (lb , ub byte access) t rc t ax t ax t aa low t ba t ba t ba t blz t oh t blz t oh t oh t blz t bhz t bhz t bhz ce1 , oe lb dq 8 to dq 1 dq 16 to dq 9 ub note : ce2 and we must be high for entire read cycle. (output) address valid data output address valid (output) valid data output valid data output
mb82dps02183b -85/-85l 18 (4) read timing #4 (page address access after ce 1 control access) t rc t rc t prc t prc t prc t paa t paa t paa t chah t oh t oh t oh t oh t clz t asc t chz t ce ce1 oe ( a 2 to a 0 ) ( a 20 to a 3 ) dq lb , ub note : ce2 and we must be high for entire read cycle. address address valid (output) valid data output (normal access) address valid data output (page access) address valid address valid address valid address valid
mb82dps02183b -85/-85l 19 (5) read timing #5 (random and page address access) t rc t rc t rc t aa l ow t paa t prc ( a 20 to a 3 ) t aso t oe t ba t olz t blz t oh t oh t oh t oh t aa t rc t paa t prc ( a 2 to a 0 ) t ax t ax ce1 oe lb , ub dq notes : ce2 and we must be high for entire read cycle. either or both lb and ub must be low when both ce 1 and oe are low. address address valid (output) valid data output (normal access) address valid data output (page access) address valid address valid address valid address valid address valid
mb82dps02183b -85/-85l 20 (6) write timing #1 (basic timing) ce1 we lb, ub oe dq t wc t wrc t wr t br t as t as t as t cw t wp t bw t as t as t ohcl t as t ds t dh note : ce2 must be high for write cycle. (input) address address valid valid data input
mb82dps02183b -85/-85l 21 (7) write timing #2 (we control) ce1 we lb, ub oe dq t wc t wc t wr t as t wp t wr t wp t as t ohah t oes t ohz t ds t dh t ds t dh low note : ce2 must be high for write cycle. (input) address address valid valid data input address valid valid data input
mb82dps02183b -85/-85l 22 (8) write timing #3-1 (we , lb , ub byte write control) ce1 we ub dq 8 to dq 1 dq 16 to dq 9 lb t wc t wc t as t wp t br t wp t as t ds t dh t ds t dh low t bs t br t bh t bs t bh note : ce2 must be high for write cycle. ( input ) address address valid valid data input address valid (input) valid data input
mb82dps02183b -85/-85l 23 (9) write timing #3-2 (we , lb , ub byte write control) ce1 we ub dq 8 to dq 1 dq 16 to dq 9 lb t wc t wc t wr t as t bw t wr t bw t ds t dh t ds t dh low t bs t bs t as t bh t bh note : ce2 must be high for write cycle. (input) address address valid valid data input address valid (input) valid data input
mb82dps02183b -85/-85l 24 (10) write timing #3-3 (we , lb , ub byte write control) ce1 we ub dq 8 to dq 1 dq 16 to dq 9 lb t wc t wc t as t bw t br t bw t ds t dh t ds t dh low t bs t bs t bh t bh t as t br note : ce2 must be high for write cycle. (input) address address valid valid data input address valid (input) valid data input
mb82dps02183b -85/-85l 25 (11) write timing #3-4 (we , lb , ub byte write control) ce1 we ub dq 8 to dq 1 dq 16 to dq 9 lb t wc t wc t br t bw t bwo t bwo t as t br t bw t as t br t bw t as t br t bw t as t ds t dh t ds t dh t ds t dh t ds t dh low note : ce2 must be high for write cycle. (input) address address valid valid data input address valid (input) valid data input valid data input valid data input
mb82dps02183b -85/-85l 26 (12) read / write timing #1-1 (ce 1 control) ce1 we ub, lb oe dq t chah t as t cp t ohcl t chz t oh t wc t cw t wrc t asc t cp t ds t dh t rc t ce t chah t clz t oh note : write address is valid from either ce 1 or we of last falling edge. address write address write data input read address read data output
mb82dps02183b -85/-85l 27 (13) read / write timing #1-2 (ce 1, we , oe control) ce1 we ub, lb oe dq t chah t as t cp t ohcl t chz t oh t wc t wp t wr t asc t cp t oe t ds t dh t rc t ce t chah t olz t oh note : oe can be fixed low during write operation if it is ce 1 controlled write at read-write-read sequence. address write address write data input read address read data output read data output
mb82dps02183b -85/-85l 28 (14) read / write timing #2 (oe , we control) ce1 we ub, lb oe dq t ohah t wr t as t oes t ohz t oh t wc t wp t oe t ohz t ds t dh t rc t aa t ohah t olz t aso t oh low note : ce 1 can be tied to low for we and oe controlled operation. address write address write data input read address read data output read data output
mb82dps02183b -85/-85l 29 (15) read / write timing #3 (oe , we , lb , ub control) (16) power-up timing ce1 we ub, lb oe dq t ohah t as t br t oes t bhz t oh t wc t bw t ba t bhz t ds t dh t rc t aa t ohah t blz t aso t oh low note : ce 1 can be tied to low for we and oe controlled operation. address read address write data input write address read data output read data output ce1 ce2 v dd 0 v v dd min t chh note : the t chh specifies after v dd reaches specified minimum level and applicable both ce 1 and ce2.
mb82dps02183b -85/-85l 30 (17) power down entry and exit timing (18) standby entry timing after read or write t chs t chh (t chhp ) t c2lp t csp power down entry power down mode power down exit high-z ce1 ce2 dq note : this power down mode can be also used as a reset timing if (16) power-up timing could not be satisfied and power down program was not performed prior to this reset. t chox t chwx active ( read ) standby active ( write ) standby ce1 oe we note : both t chox and t chwx define the earliest entry timing for standby mode. if either of timing is not satisfied, it takes t rc (min) period for standby mode from ce 1 low to high transition.
mb82dps02183b -85/-85l 31 (19) power down program timing ce1 we lb, ub oe dq* 3 t rc t rc t wc t wc t wc t wc t cp t cp t cp t cp t cp t cp * 4 rda rda rda 00 key* 3 rdb msb* 1 msb* 1 msb* 1 msb* 1 msb* 1 key* 2 address cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6 *1 : the all address inputs must be high from cycle #1 to #5. *2 : the address key must confirm the format specified in n power down. if not, the operation and data are not guaranteed. *3 : the data key must confirm the format specified in n power down. if not, the operation and data are not guaranteed. *4 : after t cp following cycle #6, the power down program is completed and returned to the normal operation.
mb82dps02183b -85/-85l 32 n ordering information part no. package remarks mb82dps02183b-85pbn 48 - ball plastic fbga 0.75 mm pitch ( bga - 48p - m18 ) t ce = 85 ns max, i dds1 = 200 m a max MB82DPS02183B-85LPBN t ce = 85 ns max, i dds1 = 100 m a max
mb82dps02183b -85/-85l 33 n package dimension 48-ball plastic fbga (bga-48p-m18) dimensions in mm (inches) note : the values in parentheses are reference values. c 2001 fujitsu limited b48018s-c-1-1 9.00 0.10(.354 .004) 6.00 0.10 (.236 .004) 0.25 0.10 (.010 .004) .041 C .004 +.006 C 0.10 +0.15 1.05 index area (mounting height) (stand off) 0.10(.004) 0.20(.008) s s (5.25(.207)) (3.75(.148)) 0.75(.030) typ 0.75(.030) typ 6 5 4 3 2 1 h g fedcb 48-?0.35 0.10 (48-?.014 .004) m 0.08(.003) s a index mark
mb82dps02183b -85/-85l fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0312 ? fujitsu limited printed in japan

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